require '_h2ph_pre.ph';

no warnings qw(redefine misc);

unless(defined(&_IF_VTEREG_H)) {
    eval 'sub _IF_VTEREG_H () {1;}' unless defined(&_IF_VTEREG_H);
    eval 'sub VTE_PCI_LOIO () {0x10;}' unless defined(&VTE_PCI_LOIO);
    eval 'sub VTE_PCI_LOMEM () {0x14;}' unless defined(&VTE_PCI_LOMEM);
    eval 'sub VTE_MCR0 () {0x;}' unless defined(&VTE_MCR0);
    eval 'sub MCR0_ACCPT_ERR () {0x1;}' unless defined(&MCR0_ACCPT_ERR);
    eval 'sub MCR0_RX_ENB () {0x2;}' unless defined(&MCR0_RX_ENB);
    eval 'sub MCR0_ACCPT_RUNT () {0x4;}' unless defined(&MCR0_ACCPT_RUNT);
    eval 'sub MCR0_ACCPT_LONG_PKT () {0x8;}' unless defined(&MCR0_ACCPT_LONG_PKT);
    eval 'sub MCR0_ACCPT_DRIBBLE () {0x10;}' unless defined(&MCR0_ACCPT_DRIBBLE);
    eval 'sub MCR0_PROMISC () {0x20;}' unless defined(&MCR0_PROMISC);
    eval 'sub MCR0_BROADCAST_DIS () {0x40;}' unless defined(&MCR0_BROADCAST_DIS);
    eval 'sub MCR0_RX_EARLY_INTR () {0x80;}' unless defined(&MCR0_RX_EARLY_INTR);
    eval 'sub MCR0_MULTICAST () {0x100;}' unless defined(&MCR0_MULTICAST);
    eval 'sub MCR0_FC_ENB () {0x200;}' unless defined(&MCR0_FC_ENB);
    eval 'sub MCR0_TX_ENB () {0x1000;}' unless defined(&MCR0_TX_ENB);
    eval 'sub MCR0_TX_EARLY_INTR () {0x4000;}' unless defined(&MCR0_TX_EARLY_INTR);
    eval 'sub MCR0_FULL_DUPLEX () {0x8000;}' unless defined(&MCR0_FULL_DUPLEX);
    eval 'sub VTE_MCR1 () {0x4;}' unless defined(&VTE_MCR1);
    eval 'sub MCR1_MAC_RESET () {0x1;}' unless defined(&MCR1_MAC_RESET);
    eval 'sub MCR1_MAC_LOOPBACK () {0x2;}' unless defined(&MCR1_MAC_LOOPBACK);
    eval 'sub MCR1_EXCESS_COL_RETRANS_DIS () {0x4;}' unless defined(&MCR1_EXCESS_COL_RETRANS_DIS);
    eval 'sub MCR1_AUTO_CHG_DUPLEX () {0x8;}' unless defined(&MCR1_AUTO_CHG_DUPLEX);
    eval 'sub MCR1_PKT_LENGTH_1518 () {0x10;}' unless defined(&MCR1_PKT_LENGTH_1518);
    eval 'sub MCR1_PKT_LENGTH_1522 () {0x20;}' unless defined(&MCR1_PKT_LENGTH_1522);
    eval 'sub MCR1_PKT_LENGTH_1534 () {0x30;}' unless defined(&MCR1_PKT_LENGTH_1534);
    eval 'sub MCR1_PKT_LENGTH_1537 () {0x;}' unless defined(&MCR1_PKT_LENGTH_1537);
    eval 'sub MCR1_EARLY_INTR_THRESH_1129 () {0x;}' unless defined(&MCR1_EARLY_INTR_THRESH_1129);
    eval 'sub MCR1_EARLY_INTR_THRESH_1257 () {0x40;}' unless defined(&MCR1_EARLY_INTR_THRESH_1257);
    eval 'sub MCR1_EARLY_INTR_THRESH_1385 () {0x80;}' unless defined(&MCR1_EARLY_INTR_THRESH_1385);
    eval 'sub MCR1_EARLY_INTR_THRESH_1513 () {0xc0;}' unless defined(&MCR1_EARLY_INTR_THRESH_1513);
    eval 'sub MCR1_EXCESS_COL_RETRY_16 () {0x;}' unless defined(&MCR1_EXCESS_COL_RETRY_16);
    eval 'sub MCR1_EXCESS_COL_RETRY_32 () {0x100;}' unless defined(&MCR1_EXCESS_COL_RETRY_32);
    eval 'sub MCR1_FC_ACTIVE () {0x200;}' unless defined(&MCR1_FC_ACTIVE);
    eval 'sub MCR1_RX_DESC_HASH_IDX () {0x4000;}' unless defined(&MCR1_RX_DESC_HASH_IDX);
    eval 'sub MCR1_RX_UNICAST_HASH () {0x8000;}' unless defined(&MCR1_RX_UNICAST_HASH);
    eval 'sub MCR1_PKT_LENGTH_MASK () {0x30;}' unless defined(&MCR1_PKT_LENGTH_MASK);
    eval 'sub MCR1_EARLY_INTR_THRESH_MASK () {0xc0;}' unless defined(&MCR1_EARLY_INTR_THRESH_MASK);
    eval 'sub VTE_MBCR () {0x8;}' unless defined(&VTE_MBCR);
    eval 'sub MBCR_FIFO_XFER_LENGTH_4 () {0x;}' unless defined(&MBCR_FIFO_XFER_LENGTH_4);
    eval 'sub MBCR_FIFO_XFER_LENGTH_8 () {0x1;}' unless defined(&MBCR_FIFO_XFER_LENGTH_8);
    eval 'sub MBCR_FIFO_XFER_LENGTH_16 () {0x2;}' unless defined(&MBCR_FIFO_XFER_LENGTH_16);
    eval 'sub MBCR_FIFO_XFER_LENGTH_32 () {0x3;}' unless defined(&MBCR_FIFO_XFER_LENGTH_32);
    eval 'sub MBCR_TX_FIFO_THRESH_16 () {0x;}' unless defined(&MBCR_TX_FIFO_THRESH_16);
    eval 'sub MBCR_TX_FIFO_THRESH_32 () {0x4;}' unless defined(&MBCR_TX_FIFO_THRESH_32);
    eval 'sub MBCR_TX_FIFO_THRESH_64 () {0x8;}' unless defined(&MBCR_TX_FIFO_THRESH_64);
    eval 'sub MBCR_TX_FIFO_THRESH_96 () {0xc;}' unless defined(&MBCR_TX_FIFO_THRESH_96);
    eval 'sub MBCR_RX_FIFO_THRESH_8 () {0x;}' unless defined(&MBCR_RX_FIFO_THRESH_8);
    eval 'sub MBCR_RX_FIFO_THRESH_16 () {0x10;}' unless defined(&MBCR_RX_FIFO_THRESH_16);
    eval 'sub MBCR_RX_FIFO_THRESH_32 () {0x20;}' unless defined(&MBCR_RX_FIFO_THRESH_32);
    eval 'sub MBCR_RX_FIFO_THRESH_64 () {0x30;}' unless defined(&MBCR_RX_FIFO_THRESH_64);
    eval 'sub MBCR_SDRAM_BUS_REQ_TIMER_MASK () {0x1f00;}' unless defined(&MBCR_SDRAM_BUS_REQ_TIMER_MASK);
    eval 'sub MBCR_SDRAM_BUS_REQ_TIMER_SHIFT () {8;}' unless defined(&MBCR_SDRAM_BUS_REQ_TIMER_SHIFT);
    eval 'sub MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT () {0x1f00;}' unless defined(&MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT);
    eval 'sub VTE_MTICR () {0xc;}' unless defined(&VTE_MTICR);
    eval 'sub MTICR_TX_TIMER_MASK () {0x1f;}' unless defined(&MTICR_TX_TIMER_MASK);
    eval 'sub MTICR_TX_BUNDLE_MASK () {0xf00;}' unless defined(&MTICR_TX_BUNDLE_MASK);
    eval 'sub VTE_IM_TX_TIMER_DEFAULT () {0x7f;}' unless defined(&VTE_IM_TX_TIMER_DEFAULT);
    eval 'sub VTE_IM_TX_BUNDLE_DEFAULT () {15;}' unless defined(&VTE_IM_TX_BUNDLE_DEFAULT);
    eval 'sub VTE_IM_TIMER_MIN () {0;}' unless defined(&VTE_IM_TIMER_MIN);
    eval 'sub VTE_IM_TIMER_MAX () {82;}' unless defined(&VTE_IM_TIMER_MAX);
    eval 'sub VTE_IM_TIMER_MASK () {0x1f;}' unless defined(&VTE_IM_TIMER_MASK);
    eval 'sub VTE_IM_TIMER_SHIFT () {0;}' unless defined(&VTE_IM_TIMER_SHIFT);
    eval 'sub VTE_IM_BUNDLE_MIN () {1;}' unless defined(&VTE_IM_BUNDLE_MIN);
    eval 'sub VTE_IM_BUNDLE_MAX () {15;}' unless defined(&VTE_IM_BUNDLE_MAX);
    eval 'sub VTE_IM_BUNDLE_SHIFT () {8;}' unless defined(&VTE_IM_BUNDLE_SHIFT);
    eval 'sub VTE_MRICR () {0x10;}' unless defined(&VTE_MRICR);
    eval 'sub MRICR_RX_TIMER_MASK () {0x1f;}' unless defined(&MRICR_RX_TIMER_MASK);
    eval 'sub MRICR_RX_BUNDLE_MASK () {0xf00;}' unless defined(&MRICR_RX_BUNDLE_MASK);
    eval 'sub VTE_IM_RX_TIMER_DEFAULT () {0x7f;}' unless defined(&VTE_IM_RX_TIMER_DEFAULT);
    eval 'sub VTE_IM_RX_BUNDLE_DEFAULT () {15;}' unless defined(&VTE_IM_RX_BUNDLE_DEFAULT);
    eval 'sub VTE_TX_POLL () {0x14;}' unless defined(&VTE_TX_POLL);
    eval 'sub TX_POLL_START () {0x1;}' unless defined(&TX_POLL_START);
    eval 'sub VTE_MRBSR () {0x18;}' unless defined(&VTE_MRBSR);
    eval 'sub VTE_MRBSR_SIZE_MASK () {0x3ff;}' unless defined(&VTE_MRBSR_SIZE_MASK);
    eval 'sub VTE_MRDCR () {0x1a;}' unless defined(&VTE_MRDCR);
    eval 'sub VTE_MRDCR_RESIDUE_MASK () {0xff;}' unless defined(&VTE_MRDCR_RESIDUE_MASK);
    eval 'sub VTE_MRDCR_RX_PAUSE_THRESH_MASK () {0xff00;}' unless defined(&VTE_MRDCR_RX_PAUSE_THRESH_MASK);
    eval 'sub VTE_MRDCR_RX_PAUSE_THRESH_SHIFT () {8;}' unless defined(&VTE_MRDCR_RX_PAUSE_THRESH_SHIFT);
    eval 'sub VTE_MLSR () {0x1c;}' unless defined(&VTE_MLSR);
    eval 'sub MLSR_MULTICAST () {0x1;}' unless defined(&MLSR_MULTICAST);
    eval 'sub MLSR_BROADCAST () {0x2;}' unless defined(&MLSR_BROADCAST);
    eval 'sub MLSR_CRC_ERR () {0x4;}' unless defined(&MLSR_CRC_ERR);
    eval 'sub MLSR_RUNT () {0x8;}' unless defined(&MLSR_RUNT);
    eval 'sub MLSR_LONG_PKT () {0x10;}' unless defined(&MLSR_LONG_PKT);
    eval 'sub MLSR_TRUNC () {0x20;}' unless defined(&MLSR_TRUNC);
    eval 'sub MLSR_DRIBBLE () {0x40;}' unless defined(&MLSR_DRIBBLE);
    eval 'sub MLSR_PHY_ERR () {0x80;}' unless defined(&MLSR_PHY_ERR);
    eval 'sub MLSR_TX_FIFO_UNDERRUN () {0x200;}' unless defined(&MLSR_TX_FIFO_UNDERRUN);
    eval 'sub MLSR_RX_DESC_UNAVAIL () {0x400;}' unless defined(&MLSR_RX_DESC_UNAVAIL);
    eval 'sub MLSR_TX_EXCESS_COL () {0x2000;}' unless defined(&MLSR_TX_EXCESS_COL);
    eval 'sub MLSR_TX_LATE_COL () {0x4000;}' unless defined(&MLSR_TX_LATE_COL);
    eval 'sub MLSR_RX_FIFO_OVERRUN () {0x8000;}' unless defined(&MLSR_RX_FIFO_OVERRUN);
    eval 'sub VTE_MMDIO () {0x20;}' unless defined(&VTE_MMDIO);
    eval 'sub MMDIO_REG_ADDR_MASK () {0x1f;}' unless defined(&MMDIO_REG_ADDR_MASK);
    eval 'sub MMDIO_PHY_ADDR_MASK () {0x1f00;}' unless defined(&MMDIO_PHY_ADDR_MASK);
    eval 'sub MMDIO_READ () {0x2000;}' unless defined(&MMDIO_READ);
    eval 'sub MMDIO_WRITE () {0x4000;}' unless defined(&MMDIO_WRITE);
    eval 'sub MMDIO_REG_ADDR_SHIFT () {0;}' unless defined(&MMDIO_REG_ADDR_SHIFT);
    eval 'sub MMDIO_PHY_ADDR_SHIFT () {8;}' unless defined(&MMDIO_PHY_ADDR_SHIFT);
    eval 'sub VTE_MMRD () {0x24;}' unless defined(&VTE_MMRD);
    eval 'sub MMRD_DATA_MASK () {0xffff;}' unless defined(&MMRD_DATA_MASK);
    eval 'sub VTE_MMWD () {0x28;}' unless defined(&VTE_MMWD);
    eval 'sub MMWD_DATA_MASK () {0xffff;}' unless defined(&MMWD_DATA_MASK);
    eval 'sub VTE_MTDSA0 () {0x2c;}' unless defined(&VTE_MTDSA0);
    eval 'sub VTE_MTDSA1 () {0x30;}' unless defined(&VTE_MTDSA1);
    eval 'sub VTE_MRDSA0 () {0x34;}' unless defined(&VTE_MRDSA0);
    eval 'sub VTE_MRDSA1 () {0x38;}' unless defined(&VTE_MRDSA1);
    eval 'sub VTE_MISR () {0x3c;}' unless defined(&VTE_MISR);
    eval 'sub MISR_RX_DONE () {0x1;}' unless defined(&MISR_RX_DONE);
    eval 'sub MISR_RX_DESC_UNAVAIL () {0x2;}' unless defined(&MISR_RX_DESC_UNAVAIL);
    eval 'sub MISR_RX_FIFO_FULL () {0x4;}' unless defined(&MISR_RX_FIFO_FULL);
    eval 'sub MISR_RX_EARLY_INTR () {0x8;}' unless defined(&MISR_RX_EARLY_INTR);
    eval 'sub MISR_TX_DONE () {0x10;}' unless defined(&MISR_TX_DONE);
    eval 'sub MISR_TX_EARLY_INTR () {0x80;}' unless defined(&MISR_TX_EARLY_INTR);
    eval 'sub MISR_EVENT_CNT_OFLOW () {0x100;}' unless defined(&MISR_EVENT_CNT_OFLOW);
    eval 'sub MISR_PHY_MEDIA_CHG () {0x200;}' unless defined(&MISR_PHY_MEDIA_CHG);
    eval 'sub VTE_MIER () {0x40;}' unless defined(&VTE_MIER);
    eval 'sub VTE_INTRS () {( &MISR_RX_DONE |  &MISR_RX_DESC_UNAVAIL |  &MISR_RX_FIFO_FULL |  &MISR_TX_DONE |  &MISR_EVENT_CNT_OFLOW);}' unless defined(&VTE_INTRS);
    eval 'sub VTE_MECISR () {0x44;}' unless defined(&VTE_MECISR);
    eval 'sub MECISR_EC_RX_DONE () {0x1;}' unless defined(&MECISR_EC_RX_DONE);
    eval 'sub MECISR_EC_MULTICAST () {0x2;}' unless defined(&MECISR_EC_MULTICAST);
    eval 'sub MECISR_EC_BROADCAST () {0x4;}' unless defined(&MECISR_EC_BROADCAST);
    eval 'sub MECISR_EC_CRC_ERR () {0x8;}' unless defined(&MECISR_EC_CRC_ERR);
    eval 'sub MECISR_EC_RUNT () {0x10;}' unless defined(&MECISR_EC_RUNT);
    eval 'sub MESCIR_EC_LONG_PKT () {0x20;}' unless defined(&MESCIR_EC_LONG_PKT);
    eval 'sub MESCIR_EC_RX_DESC_UNAVAIL () {0x80;}' unless defined(&MESCIR_EC_RX_DESC_UNAVAIL);
    eval 'sub MESCIR_EC_RX_FIFO_FULL () {0x100;}' unless defined(&MESCIR_EC_RX_FIFO_FULL);
    eval 'sub MESCIR_EC_TX_DONE () {0x200;}' unless defined(&MESCIR_EC_TX_DONE);
    eval 'sub MESCIR_EC_LATE_COL () {0x400;}' unless defined(&MESCIR_EC_LATE_COL);
    eval 'sub MESCIR_EC_TX_UNDERRUN () {0x800;}' unless defined(&MESCIR_EC_TX_UNDERRUN);
    eval 'sub VTE_MECIER () {0x48;}' unless defined(&VTE_MECIER);
    eval 'sub VTE_MECIER_INTRS () {( &MECISR_EC_RX_DONE |  &MECISR_EC_MULTICAST |  &MECISR_EC_BROADCAST |  &MECISR_EC_CRC_ERR |  &MECISR_EC_RUNT |  &MESCIR_EC_LONG_PKT |  &MESCIR_EC_RX_DESC_UNAVAIL |  &MESCIR_EC_RX_FIFO_FULL |  &MESCIR_EC_TX_DONE |  &MESCIR_EC_LATE_COL |  &MESCIR_EC_TX_UNDERRUN);}' unless defined(&VTE_MECIER_INTRS);
    eval 'sub VTE_CNT_RX_DONE () {0x50;}' unless defined(&VTE_CNT_RX_DONE);
    eval 'sub VTE_CNT_MECNT0 () {0x52;}' unless defined(&VTE_CNT_MECNT0);
    eval 'sub VTE_CNT_MECNT1 () {0x54;}' unless defined(&VTE_CNT_MECNT1);
    eval 'sub VTE_CNT_MECNT2 () {0x56;}' unless defined(&VTE_CNT_MECNT2);
    eval 'sub VTE_CNT_MECNT3 () {0x58;}' unless defined(&VTE_CNT_MECNT3);
    eval 'sub VTE_CNT_TX_DONE () {0x5a;}' unless defined(&VTE_CNT_TX_DONE);
    eval 'sub VTE_CNT_MECNT4 () {0x5c;}' unless defined(&VTE_CNT_MECNT4);
    eval 'sub VTE_CNT_PAUSE () {0x5e;}' unless defined(&VTE_CNT_PAUSE);
    eval 'sub VTE_MAR0 () {0x60;}' unless defined(&VTE_MAR0);
    eval 'sub VTE_MAR1 () {0x62;}' unless defined(&VTE_MAR1);
    eval 'sub VTE_MAR2 () {0x64;}' unless defined(&VTE_MAR2);
    eval 'sub VTE_MAR3 () {0x66;}' unless defined(&VTE_MAR3);
    eval 'sub VTE_MID0L () {0x68;}' unless defined(&VTE_MID0L);
    eval 'sub VTE_MID0M () {0x6a;}' unless defined(&VTE_MID0M);
    eval 'sub VTE_MID0H () {0x6c;}' unless defined(&VTE_MID0H);
    eval 'sub VTE_MID1L () {0x70;}' unless defined(&VTE_MID1L);
    eval 'sub VTE_MID1M () {0x72;}' unless defined(&VTE_MID1M);
    eval 'sub VTE_MID1H () {0x74;}' unless defined(&VTE_MID1H);
    eval 'sub VTE_MID2L () {0x78;}' unless defined(&VTE_MID2L);
    eval 'sub VTE_MID2M () {0x7a;}' unless defined(&VTE_MID2M);
    eval 'sub VTE_MID2H () {0x7c;}' unless defined(&VTE_MID2H);
    eval 'sub VTE_MID3L () {0x80;}' unless defined(&VTE_MID3L);
    eval 'sub VTE_MID3M () {0x82;}' unless defined(&VTE_MID3M);
    eval 'sub VTE_MID3H () {0x84;}' unless defined(&VTE_MID3H);
    eval 'sub VTE_RXFILTER_PEEFECT_BASE () { &VTE_MID1L;}' unless defined(&VTE_RXFILTER_PEEFECT_BASE);
    eval 'sub VTE_RXFILT_PERFECT_CNT () {3;}' unless defined(&VTE_RXFILT_PERFECT_CNT);
    eval 'sub VTE_MPSCCR () {0x88;}' unless defined(&VTE_MPSCCR);
    eval 'sub MPSCCR_TIMER_DIVIDER_MASK () {0x7;}' unless defined(&MPSCCR_TIMER_DIVIDER_MASK);
    eval 'sub MPSCCR_PHY_ADDR_MASK () {0x1f00;}' unless defined(&MPSCCR_PHY_ADDR_MASK);
    eval 'sub MPSCCR_PHY_STS_CHG_ENB () {0x8000;}' unless defined(&MPSCCR_PHY_STS_CHG_ENB);
    eval 'sub MPSCCR_PHY_ADDR_SHIFT () {8;}' unless defined(&MPSCCR_PHY_ADDR_SHIFT);
    eval 'sub VTE_MPSR () {0x8a;}' unless defined(&VTE_MPSR);
    eval 'sub MPSR_LINK_UP () {0x1;}' unless defined(&MPSR_LINK_UP);
    eval 'sub MPSR_SPEED_100 () {0x2;}' unless defined(&MPSR_SPEED_100);
    eval 'sub MPSR_FULL_DUPLEX () {0x4;}' unless defined(&MPSR_FULL_DUPLEX);
    eval 'sub VTE_MACSM () {0xac;}' unless defined(&VTE_MACSM);
    eval 'sub VTE_MDCSC () {0xb6;}' unless defined(&VTE_MDCSC);
    eval 'sub MDCSC_DEFAULT () {0x30;}' unless defined(&MDCSC_DEFAULT);
    eval 'sub VTE_MACID_REV () {0xbc;}' unless defined(&VTE_MACID_REV);
    eval 'sub VTE_MACID_REV_MASK () {0xff;}' unless defined(&VTE_MACID_REV_MASK);
    eval 'sub VTE_MACID_MASK () {0xff00;}' unless defined(&VTE_MACID_MASK);
    eval 'sub VTE_MACID_REV_SHIFT () {0;}' unless defined(&VTE_MACID_REV_SHIFT);
    eval 'sub VTE_MACID_SHIFT () {8;}' unless defined(&VTE_MACID_SHIFT);
    eval 'sub VTE_MACID () {0xbe;}' unless defined(&VTE_MACID);
    eval 'sub VTE_DRST_MID_MASK () {0x3;}' unless defined(&VTE_DRST_MID_MASK);
    eval 'sub VTE_DRST_MID_HIT () {0x4;}' unless defined(&VTE_DRST_MID_HIT);
    eval 'sub VTE_DRST_MULTICAST_HIT () {0x8;}' unless defined(&VTE_DRST_MULTICAST_HIT);
    eval 'sub VTE_DRST_MULTICAST () {0x10;}' unless defined(&VTE_DRST_MULTICAST);
    eval 'sub VTE_DRST_BROADCAST () {0x20;}' unless defined(&VTE_DRST_BROADCAST);
    eval 'sub VTE_DRST_CRC_ERR () {0x40;}' unless defined(&VTE_DRST_CRC_ERR);
    eval 'sub VTE_DRST_RUNT () {0x80;}' unless defined(&VTE_DRST_RUNT);
    eval 'sub VTE_DRST_LONG () {0x100;}' unless defined(&VTE_DRST_LONG);
    eval 'sub VTE_DRST_TRUNC () {0x200;}' unless defined(&VTE_DRST_TRUNC);
    eval 'sub VTE_DRST_DRIBBLE () {0x400;}' unless defined(&VTE_DRST_DRIBBLE);
    eval 'sub VTE_DRST_PHY_ERR () {0x800;}' unless defined(&VTE_DRST_PHY_ERR);
    eval 'sub VTE_DRST_RX_OK () {0x4000;}' unless defined(&VTE_DRST_RX_OK);
    eval 'sub VTE_DRST_RX_OWN () {0x8000;}' unless defined(&VTE_DRST_RX_OWN);
    eval 'sub VTE_RX_LEN {
        my($x) = @_;
	    eval q((($x) & 0x7ff));
    }' unless defined(&VTE_RX_LEN);
    eval 'sub VTE_RX_HIDX {
        my($x) = @_;
	    eval q((($x) & 0x3f));
    }' unless defined(&VTE_RX_HIDX);
    eval 'sub VTE_DTST_EXCESS_COL () {0x10;}' unless defined(&VTE_DTST_EXCESS_COL);
    eval 'sub VTE_DTST_LATE_COL () {0x20;}' unless defined(&VTE_DTST_LATE_COL);
    eval 'sub VTE_DTST_UNDERRUN () {0x40;}' unless defined(&VTE_DTST_UNDERRUN);
    eval 'sub VTE_DTST_NO_CRC () {0x2000;}' unless defined(&VTE_DTST_NO_CRC);
    eval 'sub VTE_DTST_TX_OK () {0x4000;}' unless defined(&VTE_DTST_TX_OK);
    eval 'sub VTE_DTST_TX_OWN () {0x8000;}' unless defined(&VTE_DTST_TX_OWN);
    eval 'sub VTE_TX_LEN {
        my($x) = @_;
	    eval q((($x) & 0x7ff));
    }' unless defined(&VTE_TX_LEN);
    eval 'sub VTE_TX_RING_CNT () {64;}' unless defined(&VTE_TX_RING_CNT);
    eval 'sub VTE_TX_RING_ALIGN () {16;}' unless defined(&VTE_TX_RING_ALIGN);
    eval 'sub VTE_RX_RING_CNT () {128;}' unless defined(&VTE_RX_RING_CNT);
    eval 'sub VTE_RX_RING_ALIGN () {16;}' unless defined(&VTE_RX_RING_ALIGN);
    eval 'sub VTE_RX_BUF_ALIGN () {4;}' unless defined(&VTE_RX_BUF_ALIGN);
    eval 'sub VTE_DESC_INC {
        my($x, $y) = @_;
	    eval q((($x) = (($x) + 1) % ($y)));
    }' unless defined(&VTE_DESC_INC);
    eval 'sub VTE_TX_RING_SZ () {($sizeof{\'struct vte_tx_desc\'} *  &VTE_TX_RING_CNT);}' unless defined(&VTE_TX_RING_SZ);
    eval 'sub VTE_RX_RING_SZ () {($sizeof{\'struct vte_rx_desc\'} *  &VTE_RX_RING_CNT);}' unless defined(&VTE_RX_RING_SZ);
    eval 'sub VTE_RX_BUF_SIZE_MAX () {( &MCLBYTES - $sizeof{ &uint32_t});}' unless defined(&VTE_RX_BUF_SIZE_MAX);
    eval 'sub VTE_MIN_FRAMELEN () {( &ETHER_MIN_LEN -  &ETHER_CRC_LEN);}' unless defined(&VTE_MIN_FRAMELEN);
    eval 'sub VTE_TXMBUF () {0x1;}' unless defined(&VTE_TXMBUF);
    eval 'sub VTE_FLAG_LINK () {0x8000;}' unless defined(&VTE_FLAG_LINK);
    eval 'sub CSR_WRITE_2 {
        my($_sc, $reg, $val) = @_;
	    eval q( &bus_space_write_2(( &sc)-> &sc_mem_bt, ( &sc)-> &sc_mem_bh, ($reg), ($val)));
    }' unless defined(&CSR_WRITE_2);
    eval 'sub CSR_READ_2 {
        my($_sc, $reg) = @_;
	    eval q( &bus_space_read_2(( &sc)-> &sc_mem_bt, ( &sc)-> &sc_mem_bh, ($reg)));
    }' unless defined(&CSR_READ_2);
    eval 'sub VTE_TX_TIMEOUT () {5;}' unless defined(&VTE_TX_TIMEOUT);
    eval 'sub VTE_RESET_TIMEOUT () {100;}' unless defined(&VTE_RESET_TIMEOUT);
    eval 'sub VTE_TIMEOUT () {1000;}' unless defined(&VTE_TIMEOUT);
    eval 'sub VTE_PHY_TIMEOUT () {1000;}' unless defined(&VTE_PHY_TIMEOUT);
}
1;
