require '_h2ph_pre.ph';

no warnings qw(redefine misc);

if(defined(&__loongson__)) {
    eval 'sub SB_MSR_BASE () {0x;}' unless defined(&SB_MSR_BASE);
    eval 'sub GLIU_MSR_BASE () {0x10000000;}' unless defined(&GLIU_MSR_BASE);
    eval 'sub USB_MSR_BASE () {0x40000000;}' unless defined(&USB_MSR_BASE);
    eval 'sub IDE_MSR_BASE () {0x60000000;}' unless defined(&IDE_MSR_BASE);
    eval 'sub DIVIL_MSR_BASE () {0x80000000;}' unless defined(&DIVIL_MSR_BASE);
    eval 'sub ACC_MSR_BASE () {0xa0000000;}' unless defined(&ACC_MSR_BASE);
    eval 'sub GLCP_MSR_BASE () {0xe0000000;}' unless defined(&GLCP_MSR_BASE);
} else {
    eval 'sub SB_MSR_BASE () {0x51000000;}' unless defined(&SB_MSR_BASE);
    eval 'sub GLIU_MSR_BASE () {0x51010000;}' unless defined(&GLIU_MSR_BASE);
    eval 'sub USB_MSR_BASE () {0x51200000;}' unless defined(&USB_MSR_BASE);
    eval 'sub IDE_MSR_BASE () {0x51300000;}' unless defined(&IDE_MSR_BASE);
    eval 'sub DIVIL_MSR_BASE () {0x51400000;}' unless defined(&DIVIL_MSR_BASE);
    eval 'sub ACC_MSR_BASE () {0x51500000;}' unless defined(&ACC_MSR_BASE);
    eval 'sub GLCP_MSR_BASE () {0x51700000;}' unless defined(&GLCP_MSR_BASE);
}
unless(defined(&GLIU_GLD_MSR_CAP)) {
    sub GLIU_GLD_MSR_CAP () {	( &GLIU_MSR_BASE + 0x);}
}
unless(defined(&GLIU_GLD_MSR_CONFIG)) {
    sub GLIU_GLD_MSR_CONFIG () {	( &GLIU_MSR_BASE + 0x1);}
}
unless(defined(&GLIU_GLD_MSR_SMI)) {
    sub GLIU_GLD_MSR_SMI () {	( &GLIU_MSR_BASE + 0x2);}
}
unless(defined(&GLIU_GLD_MSR_ERROR)) {
    sub GLIU_GLD_MSR_ERROR () {	( &GLIU_MSR_BASE + 0x3);}
}
unless(defined(&GLIU_GLD_MSR_PM)) {
    sub GLIU_GLD_MSR_PM () {	( &GLIU_MSR_BASE + 0x4);}
}
unless(defined(&GLIU_GLD_MSR_DIAG)) {
    sub GLIU_GLD_MSR_DIAG () {	( &GLIU_MSR_BASE + 0x5);}
}
unless(defined(&GLIU_P2D_BM0)) {
    sub GLIU_P2D_BM0 () {	( &GLIU_MSR_BASE + 0x20);}
}
unless(defined(&GLIU_P2D_BM1)) {
    sub GLIU_P2D_BM1 () {	( &GLIU_MSR_BASE + 0x21);}
}
unless(defined(&GLIU_P2D_BM2)) {
    sub GLIU_P2D_BM2 () {	( &GLIU_MSR_BASE + 0x22);}
}
unless(defined(&GLIU_P2D_BMK0)) {
    sub GLIU_P2D_BMK0 () {	( &GLIU_MSR_BASE + 0x23);}
}
unless(defined(&GLIU_P2D_BMK1)) {
    sub GLIU_P2D_BMK1 () {	( &GLIU_MSR_BASE + 0x24);}
}
unless(defined(&GLIU_P2D_BM3)) {
    sub GLIU_P2D_BM3 () {	( &GLIU_MSR_BASE + 0x25);}
}
unless(defined(&GLIU_P2D_BM4)) {
    sub GLIU_P2D_BM4 () {	( &GLIU_MSR_BASE + 0x26);}
}
unless(defined(&GLIU_COH)) {
    sub GLIU_COH () {	( &GLIU_MSR_BASE + 0x80);}
}
unless(defined(&GLIU_PAE)) {
    sub GLIU_PAE () {	( &GLIU_MSR_BASE + 0x81);}
}
unless(defined(&GLIU_ARB)) {
    sub GLIU_ARB () {	( &GLIU_MSR_BASE + 0x82);}
}
unless(defined(&GLIU_ASMI)) {
    sub GLIU_ASMI () {	( &GLIU_MSR_BASE + 0x83);}
}
unless(defined(&GLIU_AERR)) {
    sub GLIU_AERR () {	( &GLIU_MSR_BASE + 0x84);}
}
unless(defined(&GLIU_DEBUG)) {
    sub GLIU_DEBUG () {	( &GLIU_MSR_BASE + 0x85);}
}
unless(defined(&GLIU_PHY_CAP)) {
    sub GLIU_PHY_CAP () {	( &GLIU_MSR_BASE + 0x86);}
}
unless(defined(&GLIU_NOUT_RESP)) {
    sub GLIU_NOUT_RESP () {	( &GLIU_MSR_BASE + 0x87);}
}
unless(defined(&GLIU_NOUT_WDATA)) {
    sub GLIU_NOUT_WDATA () {	( &GLIU_MSR_BASE + 0x88);}
}
unless(defined(&GLIU_WHOAMI)) {
    sub GLIU_WHOAMI () {	( &GLIU_MSR_BASE + 0x8b);}
}
unless(defined(&GLIU_SLV_DIS)) {
    sub GLIU_SLV_DIS () {	( &GLIU_MSR_BASE + 0x8c);}
}
unless(defined(&GLIU_STATISTIC_CNT0)) {
    sub GLIU_STATISTIC_CNT0 () {	( &GLIU_MSR_BASE + 0xa0);}
}
unless(defined(&GLIU_STATISTIC_MASK0)) {
    sub GLIU_STATISTIC_MASK0 () {	( &GLIU_MSR_BASE + 0xa1);}
}
unless(defined(&GLIU_STATISTIC_ACTION0)) {
    sub GLIU_STATISTIC_ACTION0 () {	( &GLIU_MSR_BASE + 0xa2);}
}
unless(defined(&GLIU_STATISTIC_CNT1)) {
    sub GLIU_STATISTIC_CNT1 () {	( &GLIU_MSR_BASE + 0xa4);}
}
unless(defined(&GLIU_STATISTIC_MASK1)) {
    sub GLIU_STATISTIC_MASK1 () {	( &GLIU_MSR_BASE + 0xa5);}
}
unless(defined(&GLIU_STATISTIC_ACTION1)) {
    sub GLIU_STATISTIC_ACTION1 () {	( &GLIU_MSR_BASE + 0xa6);}
}
unless(defined(&GLIU_STATISTIC_CNT2)) {
    sub GLIU_STATISTIC_CNT2 () {	( &GLIU_MSR_BASE + 0xa8);}
}
unless(defined(&GLIU_STATISTIC_MASK2)) {
    sub GLIU_STATISTIC_MASK2 () {	( &GLIU_MSR_BASE + 0xa9);}
}
unless(defined(&GLIU_STATISTIC_ACTION2)) {
    sub GLIU_STATISTIC_ACTION2 () {	( &GLIU_MSR_BASE + 0xaa);}
}
unless(defined(&GLIU_RQ_COMP_VAL)) {
    sub GLIU_RQ_COMP_VAL () {	( &GLIU_MSR_BASE + 0xc0);}
}
unless(defined(&GLIU_RQ_COMP_MASK)) {
    sub GLIU_RQ_COMP_MASK () {	( &GLIU_MSR_BASE + 0xc1);}
}
unless(defined(&GLIU_DA_COMP_VAL_LO)) {
    sub GLIU_DA_COMP_VAL_LO () {	( &GLIU_MSR_BASE + 0xd0);}
}
unless(defined(&GLIU_DA_COMP_VAL_HI)) {
    sub GLIU_DA_COMP_VAL_HI () {	( &GLIU_MSR_BASE + 0xd1);}
}
unless(defined(&GLIU_DA_COMP_MASK_LO)) {
    sub GLIU_DA_COMP_MASK_LO () {	( &GLIU_MSR_BASE + 0xd2);}
}
unless(defined(&GLIU_DA_COMP_MASK_HI)) {
    sub GLIU_DA_COMP_MASK_HI () {	( &GLIU_MSR_BASE + 0xd3);}
}
unless(defined(&GLIU_IOD_BM0)) {
    sub GLIU_IOD_BM0 () {	( &GLIU_MSR_BASE + 0xe0);}
}
unless(defined(&GLIU_IOD_BM1)) {
    sub GLIU_IOD_BM1 () {	( &GLIU_MSR_BASE + 0xe1);}
}
unless(defined(&GLIU_IOD_BM2)) {
    sub GLIU_IOD_BM2 () {	( &GLIU_MSR_BASE + 0xe2);}
}
unless(defined(&GLIU_IOD_BM3)) {
    sub GLIU_IOD_BM3 () {	( &GLIU_MSR_BASE + 0xe3);}
}
unless(defined(&GLIU_IOD_BM4)) {
    sub GLIU_IOD_BM4 () {	( &GLIU_MSR_BASE + 0xe4);}
}
unless(defined(&GLIU_IOD_BM5)) {
    sub GLIU_IOD_BM5 () {	( &GLIU_MSR_BASE + 0xe5);}
}
unless(defined(&GLIU_IOD_BM6)) {
    sub GLIU_IOD_BM6 () {	( &GLIU_MSR_BASE + 0xe6);}
}
unless(defined(&GLIU_IOD_BM7)) {
    sub GLIU_IOD_BM7 () {	( &GLIU_MSR_BASE + 0xe7);}
}
unless(defined(&GLIU_IOD_BM8)) {
    sub GLIU_IOD_BM8 () {	( &GLIU_MSR_BASE + 0xe8);}
}
unless(defined(&GLIU_IOD_BM9)) {
    sub GLIU_IOD_BM9 () {	( &GLIU_MSR_BASE + 0xe9);}
}
unless(defined(&GLIU_IOD_SC0)) {
    sub GLIU_IOD_SC0 () {	( &GLIU_MSR_BASE + 0xea);}
}
unless(defined(&GLIU_IOD_SC1)) {
    sub GLIU_IOD_SC1 () {	( &GLIU_MSR_BASE + 0xeb);}
}
unless(defined(&GLIU_IOD_SC2)) {
    sub GLIU_IOD_SC2 () {	( &GLIU_MSR_BASE + 0xec);}
}
unless(defined(&GLIU_IOD_SC3)) {
    sub GLIU_IOD_SC3 () {	( &GLIU_MSR_BASE + 0xed);}
}
unless(defined(&GLIU_IOD_SC4)) {
    sub GLIU_IOD_SC4 () {	( &GLIU_MSR_BASE + 0xee);}
}
unless(defined(&GLIU_IOD_SC5)) {
    sub GLIU_IOD_SC5 () {	( &GLIU_MSR_BASE + 0xef);}
}
unless(defined(&GLIU_IOD_SC6)) {
    sub GLIU_IOD_SC6 () {	( &GLIU_MSR_BASE + 0xf0);}
}
unless(defined(&GLIU_IOD_SC7)) {
    sub GLIU_IOD_SC7 () {	( &GLIU_MSR_BASE + 0xf1);}
}
unless(defined(&GLPCI_GLD_MSR_CAP)) {
    sub GLPCI_GLD_MSR_CAP () {	( &SB_MSR_BASE + 0x);}
}
unless(defined(&GLPCI_GLD_MSR_CONFIG)) {
    sub GLPCI_GLD_MSR_CONFIG () {	( &SB_MSR_BASE + 0x1);}
}
unless(defined(&GLPCI_GLD_MSR_SMI)) {
    sub GLPCI_GLD_MSR_SMI () {	( &SB_MSR_BASE + 0x2);}
}
unless(defined(&GLPCI_GLD_MSR_ERROR)) {
    sub GLPCI_GLD_MSR_ERROR () {	( &SB_MSR_BASE + 0x3);}
}
unless(defined(&GLPCI_GLD_MSR_PM)) {
    sub GLPCI_GLD_MSR_PM () {	( &SB_MSR_BASE + 0x4);}
}
unless(defined(&GLPCI_GLD_MSR_DIAG)) {
    sub GLPCI_GLD_MSR_DIAG () {	( &SB_MSR_BASE + 0x5);}
}
unless(defined(&GLPCI_CTRL)) {
    sub GLPCI_CTRL () {	( &SB_MSR_BASE + 0x10);}
}
unless(defined(&GLPCI_R0)) {
    sub GLPCI_R0 () {	( &SB_MSR_BASE + 0x20);}
}
unless(defined(&GLPCI_R1)) {
    sub GLPCI_R1 () {	( &SB_MSR_BASE + 0x21);}
}
unless(defined(&GLPCI_R2)) {
    sub GLPCI_R2 () {	( &SB_MSR_BASE + 0x22);}
}
unless(defined(&GLPCI_R3)) {
    sub GLPCI_R3 () {	( &SB_MSR_BASE + 0x23);}
}
unless(defined(&GLPCI_R4)) {
    sub GLPCI_R4 () {	( &SB_MSR_BASE + 0x24);}
}
unless(defined(&GLPCI_R5)) {
    sub GLPCI_R5 () {	( &SB_MSR_BASE + 0x25);}
}
unless(defined(&GLPCI_R6)) {
    sub GLPCI_R6 () {	( &SB_MSR_BASE + 0x26);}
}
unless(defined(&GLPCI_R7)) {
    sub GLPCI_R7 () {	( &SB_MSR_BASE + 0x27);}
}
unless(defined(&GLPCI_R8)) {
    sub GLPCI_R8 () {	( &SB_MSR_BASE + 0x28);}
}
unless(defined(&GLPCI_R9)) {
    sub GLPCI_R9 () {	( &SB_MSR_BASE + 0x29);}
}
unless(defined(&GLPCI_R10)) {
    sub GLPCI_R10 () {	( &SB_MSR_BASE + 0x2a);}
}
unless(defined(&GLPCI_R11)) {
    sub GLPCI_R11 () {	( &SB_MSR_BASE + 0x2b);}
}
unless(defined(&GLPCI_R12)) {
    sub GLPCI_R12 () {	( &SB_MSR_BASE + 0x2c);}
}
unless(defined(&GLPCI_R13)) {
    sub GLPCI_R13 () {	( &SB_MSR_BASE + 0x2d);}
}
unless(defined(&GLPCI_R14)) {
    sub GLPCI_R14 () {	( &SB_MSR_BASE + 0x2e);}
}
unless(defined(&GLPCI_R15)) {
    sub GLPCI_R15 () {	( &SB_MSR_BASE + 0x2f);}
}
unless(defined(&GLPCI_PCIHEAD_BYTE0_3)) {
    sub GLPCI_PCIHEAD_BYTE0_3 () {	( &SB_MSR_BASE + 0x30);}
}
unless(defined(&GLPCI_PCIHEAD_BYTE4_7)) {
    sub GLPCI_PCIHEAD_BYTE4_7 () {	( &SB_MSR_BASE + 0x31);}
}
unless(defined(&GLPCI_PCIHEAD_BYTE8_B)) {
    sub GLPCI_PCIHEAD_BYTE8_B () {	( &SB_MSR_BASE + 0x32);}
}
unless(defined(&GLPCI_PCIHEAD_BYTEC_F)) {
    sub GLPCI_PCIHEAD_BYTEC_F () {	( &SB_MSR_BASE + 0x33);}
}
unless(defined(&ACC_GLD_MSR_CAP)) {
    sub ACC_GLD_MSR_CAP () {	( &ACC_MSR_BASE + 0x);}
}
unless(defined(&ACC_GLD_MSR_CONFIG)) {
    sub ACC_GLD_MSR_CONFIG () {	( &ACC_MSR_BASE + 0x1);}
}
unless(defined(&ACC_GLD_MSR_SMI)) {
    sub ACC_GLD_MSR_SMI () {	( &ACC_MSR_BASE + 0x2);}
}
unless(defined(&ACC_GLD_MSR_ERROR)) {
    sub ACC_GLD_MSR_ERROR () {	( &ACC_MSR_BASE + 0x3);}
}
unless(defined(&ACC_GLD_MSR_PM)) {
    sub ACC_GLD_MSR_PM () {	( &ACC_MSR_BASE + 0x4);}
}
unless(defined(&ACC_GLD_MSR_DIAG)) {
    sub ACC_GLD_MSR_DIAG () {	( &ACC_MSR_BASE + 0x5);}
}
unless(defined(&USB_GLD_MSR_CAP)) {
    sub USB_GLD_MSR_CAP () {	( &USB_MSR_BASE + 0x);}
}
unless(defined(&USB_GLD_MSR_CONFIG)) {
    sub USB_GLD_MSR_CONFIG () {	( &USB_MSR_BASE + 0x1);}
}
unless(defined(&USB_GLD_MSR_SMI)) {
    sub USB_GLD_MSR_SMI () {	( &USB_MSR_BASE + 0x2);}
}
unless(defined(&USB_GLD_MSR_ERROR)) {
    sub USB_GLD_MSR_ERROR () {	( &USB_MSR_BASE + 0x3);}
}
unless(defined(&USB_GLD_MSR_PM)) {
    sub USB_GLD_MSR_PM () {	( &USB_MSR_BASE + 0x4);}
}
unless(defined(&USB_GLD_MSR_DIAG)) {
    sub USB_GLD_MSR_DIAG () {	( &USB_MSR_BASE + 0x5);}
}
unless(defined(&USB_MSR_OHCB)) {
    sub USB_MSR_OHCB () {	( &USB_MSR_BASE + 0x8);}
}
unless(defined(&USB_MSR_EHCB)) {
    sub USB_MSR_EHCB () {	( &USB_MSR_BASE + 0x9);}
}
unless(defined(&USB_MSR_UDCB)) {
    sub USB_MSR_UDCB () {	( &USB_MSR_BASE + 0xa);}
}
unless(defined(&USB_MSR_UOCB)) {
    sub USB_MSR_UOCB () {	( &USB_MSR_BASE + 0xb);}
}
unless(defined(&IDE_GLD_MSR_CAP)) {
    sub IDE_GLD_MSR_CAP () {	( &IDE_MSR_BASE + 0x);}
}
unless(defined(&IDE_GLD_MSR_CONFIG)) {
    sub IDE_GLD_MSR_CONFIG () {	( &IDE_MSR_BASE + 0x1);}
}
unless(defined(&IDE_GLD_MSR_SMI)) {
    sub IDE_GLD_MSR_SMI () {	( &IDE_MSR_BASE + 0x2);}
}
unless(defined(&IDE_GLD_MSR_ERROR)) {
    sub IDE_GLD_MSR_ERROR () {	( &IDE_MSR_BASE + 0x3);}
}
unless(defined(&IDE_GLD_MSR_PM)) {
    sub IDE_GLD_MSR_PM () {	( &IDE_MSR_BASE + 0x4);}
}
unless(defined(&IDE_GLD_MSR_DIAG)) {
    sub IDE_GLD_MSR_DIAG () {	( &IDE_MSR_BASE + 0x5);}
}
unless(defined(&IDE_IO_BAR)) {
    sub IDE_IO_BAR () {	( &IDE_MSR_BASE + 0x8);}
}
unless(defined(&IDE_CFG)) {
    sub IDE_CFG () {	( &IDE_MSR_BASE + 0x10);}
}
unless(defined(&IDE_DTC)) {
    sub IDE_DTC () {	( &IDE_MSR_BASE + 0x12);}
}
unless(defined(&IDE_CAST)) {
    sub IDE_CAST () {	( &IDE_MSR_BASE + 0x13);}
}
unless(defined(&IDE_ETC)) {
    sub IDE_ETC () {	( &IDE_MSR_BASE + 0x14);}
}
unless(defined(&IDE_PM)) {
    sub IDE_PM () {	( &IDE_MSR_BASE + 0x15);}
}
unless(defined(&DIVIL_GLD_MSR_CAP)) {
    sub DIVIL_GLD_MSR_CAP () {	( &DIVIL_MSR_BASE + 0x);}
}
unless(defined(&DIVIL_GLD_MSR_CONFIG)) {
    sub DIVIL_GLD_MSR_CONFIG () {	( &DIVIL_MSR_BASE + 0x1);}
}
unless(defined(&DIVIL_GLD_MSR_SMI)) {
    sub DIVIL_GLD_MSR_SMI () {	( &DIVIL_MSR_BASE + 0x2);}
}
unless(defined(&DIVIL_GLD_MSR_ERROR)) {
    sub DIVIL_GLD_MSR_ERROR () {	( &DIVIL_MSR_BASE + 0x3);}
}
unless(defined(&DIVIL_GLD_MSR_PM)) {
    sub DIVIL_GLD_MSR_PM () {	( &DIVIL_MSR_BASE + 0x4);}
}
unless(defined(&DIVIL_GLD_MSR_DIAG)) {
    sub DIVIL_GLD_MSR_DIAG () {	( &DIVIL_MSR_BASE + 0x5);}
}
unless(defined(&DIVIL_LBAR_IRQ)) {
    sub DIVIL_LBAR_IRQ () {	( &DIVIL_MSR_BASE + 0x8);}
}
unless(defined(&DIVIL_LBAR_KEL)) {
    sub DIVIL_LBAR_KEL () {	( &DIVIL_MSR_BASE + 0x9);}
}
unless(defined(&DIVIL_LBAR_SMB)) {
    sub DIVIL_LBAR_SMB () {	( &DIVIL_MSR_BASE + 0xb);}
}
unless(defined(&DIVIL_LBAR_GPIO)) {
    sub DIVIL_LBAR_GPIO () {	( &DIVIL_MSR_BASE + 0xc);}
}
unless(defined(&DIVIL_LBAR_MFGPT)) {
    sub DIVIL_LBAR_MFGPT () {	( &DIVIL_MSR_BASE + 0xd);}
}
unless(defined(&DIVIL_LBAR_ACPI)) {
    sub DIVIL_LBAR_ACPI () {	( &DIVIL_MSR_BASE + 0xe);}
}
unless(defined(&DIVIL_LBAR_PMS)) {
    sub DIVIL_LBAR_PMS () {	( &DIVIL_MSR_BASE + 0xf);}
}
unless(defined(&DIVIL_LBAR_FLSH0)) {
    sub DIVIL_LBAR_FLSH0 () {	( &DIVIL_MSR_BASE + 0x10);}
}
unless(defined(&DIVIL_LBAR_FLSH1)) {
    sub DIVIL_LBAR_FLSH1 () {	( &DIVIL_MSR_BASE + 0x11);}
}
unless(defined(&DIVIL_LBAR_FLSH2)) {
    sub DIVIL_LBAR_FLSH2 () {	( &DIVIL_MSR_BASE + 0x12);}
}
unless(defined(&DIVIL_LBAR_FLSH3)) {
    sub DIVIL_LBAR_FLSH3 () {	( &DIVIL_MSR_BASE + 0x13);}
}
unless(defined(&DIVIL_LEG_IO)) {
    sub DIVIL_LEG_IO () {	( &DIVIL_MSR_BASE + 0x14);}
}
unless(defined(&DIVIL_BALL_OPTS)) {
    sub DIVIL_BALL_OPTS () {	( &DIVIL_MSR_BASE + 0x15);}
}
unless(defined(&DIVIL_SOFT_IRQ)) {
    sub DIVIL_SOFT_IRQ () {	( &DIVIL_MSR_BASE + 0x16);}
}
unless(defined(&DIVIL_SOFT_RESET)) {
    sub DIVIL_SOFT_RESET () {	( &DIVIL_MSR_BASE + 0x17);}
}
unless(defined(&NORF_CTL)) {
    sub NORF_CTL () {	( &DIVIL_MSR_BASE + 0x18);}
}
unless(defined(&NORF_T01)) {
    sub NORF_T01 () {	( &DIVIL_MSR_BASE + 0x19);}
}
unless(defined(&NORF_T23)) {
    sub NORF_T23 () {	( &DIVIL_MSR_BASE + 0x1a);}
}
unless(defined(&NANDF_DATA)) {
    sub NANDF_DATA () {	( &DIVIL_MSR_BASE + 0x1b);}
}
unless(defined(&NANDF_CTL)) {
    sub NANDF_CTL () {	( &DIVIL_MSR_BASE + 0x1c);}
}
unless(defined(&NANDF_RSVD)) {
    sub NANDF_RSVD () {	( &DIVIL_MSR_BASE + 0x1d);}
}
unless(defined(&DIVIL_AC_DMA)) {
    sub DIVIL_AC_DMA () {	( &DIVIL_MSR_BASE + 0x1e);}
}
unless(defined(&KELX_CTL)) {
    sub KELX_CTL () {	( &DIVIL_MSR_BASE + 0x1f);}
}
unless(defined(&PIC_YSEL_LOW)) {
    sub PIC_YSEL_LOW () {	( &DIVIL_MSR_BASE + 0x20);}
}
unless(defined(&PIC_YSEL_HIGH)) {
    sub PIC_YSEL_HIGH () {	( &DIVIL_MSR_BASE + 0x21);}
}
unless(defined(&PIC_ZSEL_LOW)) {
    sub PIC_ZSEL_LOW () {	( &DIVIL_MSR_BASE + 0x22);}
}
unless(defined(&PIC_ZSEL_HIGH)) {
    sub PIC_ZSEL_HIGH () {	( &DIVIL_MSR_BASE + 0x23);}
}
unless(defined(&PIC_IRQM_PRIM)) {
    sub PIC_IRQM_PRIM () {	( &DIVIL_MSR_BASE + 0x24);}
}
unless(defined(&PIC_IRQM_LPC)) {
    sub PIC_IRQM_LPC () {	( &DIVIL_MSR_BASE + 0x25);}
}
unless(defined(&PIC_XIRR_STS_LOW)) {
    sub PIC_XIRR_STS_LOW () {	( &DIVIL_MSR_BASE + 0x26);}
}
unless(defined(&PIC_XIRR_STS_HIGH)) {
    sub PIC_XIRR_STS_HIGH () {	( &DIVIL_MSR_BASE + 0x27);}
}
unless(defined(&MFGPT_IRQ)) {
    sub MFGPT_IRQ () {	( &DIVIL_MSR_BASE + 0x28);}
}
unless(defined(&MFGPT_NR)) {
    sub MFGPT_NR () {	( &DIVIL_MSR_BASE + 0x29);}
}
unless(defined(&MFGPT_RSVD)) {
    sub MFGPT_RSVD () {	( &DIVIL_MSR_BASE + 0x2a);}
}
unless(defined(&MFGPT_SETUP)) {
    sub MFGPT_SETUP () {	( &DIVIL_MSR_BASE + 0x2b);}
}
unless(defined(&FLPY_3F2_SHDW)) {
    sub FLPY_3F2_SHDW () {	( &DIVIL_MSR_BASE + 0x30);}
}
unless(defined(&FLPY_3F7_SHDW)) {
    sub FLPY_3F7_SHDW () {	( &DIVIL_MSR_BASE + 0x31);}
}
unless(defined(&FLPY_372_SHDW)) {
    sub FLPY_372_SHDW () {	( &DIVIL_MSR_BASE + 0x32);}
}
unless(defined(&FLPY_377_SHDW)) {
    sub FLPY_377_SHDW () {	( &DIVIL_MSR_BASE + 0x33);}
}
unless(defined(&PIC_SHDW)) {
    sub PIC_SHDW () {	( &DIVIL_MSR_BASE + 0x34);}
}
unless(defined(&PIT_SHDW)) {
    sub PIT_SHDW () {	( &DIVIL_MSR_BASE + 0x36);}
}
unless(defined(&PIT_CNTRL)) {
    sub PIT_CNTRL () {	( &DIVIL_MSR_BASE + 0x37);}
}
unless(defined(&UART1_MOD)) {
    sub UART1_MOD () {	( &DIVIL_MSR_BASE + 0x38);}
}
unless(defined(&UART1_DONG)) {
    sub UART1_DONG () {	( &DIVIL_MSR_BASE + 0x39);}
}
unless(defined(&UART1_CONF)) {
    sub UART1_CONF () {	( &DIVIL_MSR_BASE + 0x3a);}
}
unless(defined(&UART1_RSVD_MSR)) {
    sub UART1_RSVD_MSR () {	( &DIVIL_MSR_BASE + 0x3b);}
}
unless(defined(&UART2_MOD)) {
    sub UART2_MOD () {	( &DIVIL_MSR_BASE + 0x3c);}
}
unless(defined(&UART2_DONG)) {
    sub UART2_DONG () {	( &DIVIL_MSR_BASE + 0x3d);}
}
unless(defined(&UART2_CONF)) {
    sub UART2_CONF () {	( &DIVIL_MSR_BASE + 0x3e);}
}
unless(defined(&UART2_RSVD_MSR)) {
    sub UART2_RSVD_MSR () {	( &DIVIL_MSR_BASE + 0x3f);}
}
unless(defined(&DMA_MAP)) {
    sub DMA_MAP () {	( &DIVIL_MSR_BASE + 0x40);}
}
unless(defined(&DMA_SHDW_CH0)) {
    sub DMA_SHDW_CH0 () {	( &DIVIL_MSR_BASE + 0x41);}
}
unless(defined(&DMA_SHDW_CH1)) {
    sub DMA_SHDW_CH1 () {	( &DIVIL_MSR_BASE + 0x42);}
}
unless(defined(&DMA_SHDW_CH2)) {
    sub DMA_SHDW_CH2 () {	( &DIVIL_MSR_BASE + 0x43);}
}
unless(defined(&DMA_SHDW_CH3)) {
    sub DMA_SHDW_CH3 () {	( &DIVIL_MSR_BASE + 0x44);}
}
unless(defined(&DMA_SHDW_CH4)) {
    sub DMA_SHDW_CH4 () {	( &DIVIL_MSR_BASE + 0x45);}
}
unless(defined(&DMA_SHDW_CH5)) {
    sub DMA_SHDW_CH5 () {	( &DIVIL_MSR_BASE + 0x46);}
}
unless(defined(&DMA_SHDW_CH6)) {
    sub DMA_SHDW_CH6 () {	( &DIVIL_MSR_BASE + 0x47);}
}
unless(defined(&DMA_SHDW_CH7)) {
    sub DMA_SHDW_CH7 () {	( &DIVIL_MSR_BASE + 0x48);}
}
unless(defined(&DMA_MSK_SHDW)) {
    sub DMA_MSK_SHDW () {	( &DIVIL_MSR_BASE + 0x49);}
}
unless(defined(&LPC_EADDR)) {
    sub LPC_EADDR () {	( &DIVIL_MSR_BASE + 0x4c);}
}
unless(defined(&LPC_ESTAT)) {
    sub LPC_ESTAT () {	( &DIVIL_MSR_BASE + 0x4d);}
}
unless(defined(&LPC_SIRQ)) {
    sub LPC_SIRQ () {	( &DIVIL_MSR_BASE + 0x4e);}
}
unless(defined(&LPC_RSVD)) {
    sub LPC_RSVD () {	( &DIVIL_MSR_BASE + 0x4f);}
}
unless(defined(&PMC_LTMR)) {
    sub PMC_LTMR () {	( &DIVIL_MSR_BASE + 0x50);}
}
unless(defined(&PMC_RSVD)) {
    sub PMC_RSVD () {	( &DIVIL_MSR_BASE + 0x51);}
}
unless(defined(&RTC_RAM_LOCK)) {
    sub RTC_RAM_LOCK () {	( &DIVIL_MSR_BASE + 0x54);}
}
unless(defined(&RTC_DOMA_OFFSET)) {
    sub RTC_DOMA_OFFSET () {	( &DIVIL_MSR_BASE + 0x55);}
}
unless(defined(&RTC_MONA_OFFSET)) {
    sub RTC_MONA_OFFSET () {	( &DIVIL_MSR_BASE + 0x56);}
}
unless(defined(&RTC_CEN_OFFSET)) {
    sub RTC_CEN_OFFSET () {	( &DIVIL_MSR_BASE + 0x57);}
}
unless(defined(&GLCP_GLD_MSR_CAP)) {
    sub GLCP_GLD_MSR_CAP () {	( &GLCP_MSR_BASE + 0x);}
}
unless(defined(&GLCP_GLD_MSR_CONFIG)) {
    sub GLCP_GLD_MSR_CONFIG () {	( &GLCP_MSR_BASE + 0x1);}
}
unless(defined(&GLCP_GLD_MSR_SMI)) {
    sub GLCP_GLD_MSR_SMI () {	( &GLCP_MSR_BASE + 0x2);}
}
unless(defined(&GLCP_GLD_MSR_ERROR)) {
    sub GLCP_GLD_MSR_ERROR () {	( &GLCP_MSR_BASE + 0x3);}
}
unless(defined(&GLCP_GLD_MSR_PM)) {
    sub GLCP_GLD_MSR_PM () {	( &GLCP_MSR_BASE + 0x4);}
}
unless(defined(&GLCP_GLD_MSR_DIAG)) {
    sub GLCP_GLD_MSR_DIAG () {	( &GLCP_MSR_BASE + 0x5);}
}
unless(defined(&GLCP_CLK_DIS_DELAY)) {
    sub GLCP_CLK_DIS_DELAY () {	( &GLCP_MSR_BASE + 0x8);}
}
unless(defined(&GLCP_PMCLKDISABLE)) {
    sub GLCP_PMCLKDISABLE () {	( &GLCP_MSR_BASE + 0x9);}
}
unless(defined(&GLCP_GLB_PM)) {
    sub GLCP_GLB_PM () {	( &GLCP_MSR_BASE + 0xb);}
}
unless(defined(&GLCP_DBGOUT)) {
    sub GLCP_DBGOUT () {	( &GLCP_MSR_BASE + 0xc);}
}
unless(defined(&GLCP_DOWSER)) {
    sub GLCP_DOWSER () {	( &GLCP_MSR_BASE + 0xe);}
}
unless(defined(&GLCP_CLKOFF)) {
    sub GLCP_CLKOFF () {	( &GLCP_MSR_BASE + 0x10);}
}
unless(defined(&GLCP_CLKACTIVE)) {
    sub GLCP_CLKACTIVE () {	( &GLCP_MSR_BASE + 0x11);}
}
unless(defined(&GLCP_CLKDISABLE)) {
    sub GLCP_CLKDISABLE () {	( &GLCP_MSR_BASE + 0x12);}
}
unless(defined(&GLCP_CLK4ACK)) {
    sub GLCP_CLK4ACK () {	( &GLCP_MSR_BASE + 0x13);}
}
unless(defined(&GLCP_SYS_RST)) {
    sub GLCP_SYS_RST () {	( &GLCP_MSR_BASE + 0x14);}
}
unless(defined(&GLCP_DBGCLKCTRL)) {
    sub GLCP_DBGCLKCTRL () {	( &GLCP_MSR_BASE + 0x16);}
}
unless(defined(&GLCP_CHIP_REV_ID)) {
    sub GLCP_CHIP_REV_ID () {	( &GLCP_MSR_BASE + 0x17);}
}
unless(defined(&GPIOL_OUT_VAL)) {
    sub GPIOL_OUT_VAL () {	0x;}
}
unless(defined(&GPIOL_OUT_EN)) {
    sub GPIOL_OUT_EN () {	0x4;}
}
unless(defined(&GPIOL_OUT_OD_EN)) {
    sub GPIOL_OUT_OD_EN () {	0x8;}
}
unless(defined(&GPIOL_OUT_INVRT_EN)) {
    sub GPIOL_OUT_INVRT_EN () {	0xc;}
}
unless(defined(&GPIOL_OUT_AUX1_SEL)) {
    sub GPIOL_OUT_AUX1_SEL () {	0x10;}
}
unless(defined(&GPIOL_OUT_AUX2_SEL)) {
    sub GPIOL_OUT_AUX2_SEL () {	0x14;}
}
unless(defined(&GPIOL_PU_EN)) {
    sub GPIOL_PU_EN () {	0x18;}
}
unless(defined(&GPIOL_PD_EN)) {
    sub GPIOL_PD_EN () {	0x1c;}
}
unless(defined(&GPIOL_IN_EN)) {
    sub GPIOL_IN_EN () {	0x20;}
}
unless(defined(&GPIOL_IN_INV_EN)) {
    sub GPIOL_IN_INV_EN () {	0x24;}
}
unless(defined(&GPIOL_IN_FLTR_EN)) {
    sub GPIOL_IN_FLTR_EN () {	0x28;}
}
unless(defined(&GPIOL_IN_EVNTCNT_EN)) {
    sub GPIOL_IN_EVNTCNT_EN () {	0x2c;}
}
unless(defined(&GPIOL_READ_BACK)) {
    sub GPIOL_READ_BACK () {	0x30;}
}
unless(defined(&GPIOL_IN_AUX1_SEL)) {
    sub GPIOL_IN_AUX1_SEL () {	0x34;}
}
unless(defined(&GPIOL_EVNT_EN)) {
    sub GPIOL_EVNT_EN () {	0x38;}
}
unless(defined(&GPIOL_LOCK_EN)) {
    sub GPIOL_LOCK_EN () {	0x3c;}
}
unless(defined(&GPIOL_POSEDGE_EN)) {
    sub GPIOL_POSEDGE_EN () {	0x40;}
}
unless(defined(&GPIOL_NEGEDGE_EN)) {
    sub GPIOL_NEGEDGE_EN () {	0x44;}
}
unless(defined(&GPIOL_POSEDGE_STS)) {
    sub GPIOL_POSEDGE_STS () {	0x48;}
}
unless(defined(&GPIOL_NEGEDGE_STS)) {
    sub GPIOL_NEGEDGE_STS () {	0x4c;}
}
unless(defined(&GPIO_FLTR0_AMNT)) {
    sub GPIO_FLTR0_AMNT () {	0x50;}
}
unless(defined(&GPIO_FLTR0_CNT)) {
    sub GPIO_FLTR0_CNT () {	0x52;}
}
unless(defined(&GPIO_EVNTCNT0)) {
    sub GPIO_EVNTCNT0 () {	0x54;}
}
unless(defined(&GPIO_EVNTCNT0_COMP)) {
    sub GPIO_EVNTCNT0_COMP () {	0x56;}
}
unless(defined(&GPIO_FLTR1_AMNT)) {
    sub GPIO_FLTR1_AMNT () {	0x58;}
}
unless(defined(&GPIO_FLTR1_CNT)) {
    sub GPIO_FLTR1_CNT () {	0x5a;}
}
unless(defined(&GPIO_EVNTCNT1)) {
    sub GPIO_EVNTCNT1 () {	0x5c;}
}
unless(defined(&GPIO_EVNTCNT1_COMP)) {
    sub GPIO_EVNTCNT1_COMP () {	0x5e;}
}
unless(defined(&GPIO_FLTR2_AMNT)) {
    sub GPIO_FLTR2_AMNT () {	0x60;}
}
unless(defined(&GPIO_FLTR2_CNT)) {
    sub GPIO_FLTR2_CNT () {	0x62;}
}
unless(defined(&GPIO_EVNTCNT2)) {
    sub GPIO_EVNTCNT2 () {	0x64;}
}
unless(defined(&GPIO_EVNTCNT2_COMP)) {
    sub GPIO_EVNTCNT2_COMP () {	0x66;}
}
unless(defined(&GPIO_FLTR3_AMNT)) {
    sub GPIO_FLTR3_AMNT () {	0x68;}
}
unless(defined(&GPIO_FLTR3_CNT)) {
    sub GPIO_FLTR3_CNT () {	0x6a;}
}
unless(defined(&GPIO_EVNTCNT3)) {
    sub GPIO_EVNTCNT3 () {	0x6c;}
}
unless(defined(&GPIO_EVNTCNT3_COMP)) {
    sub GPIO_EVNTCNT3_COMP () {	0x6e;}
}
unless(defined(&GPIO_FLTR4_AMNT)) {
    sub GPIO_FLTR4_AMNT () {	0x70;}
}
unless(defined(&GPIO_FLTR4_CNT)) {
    sub GPIO_FLTR4_CNT () {	0x72;}
}
unless(defined(&GPIO_EVNTCNT4)) {
    sub GPIO_EVNTCNT4 () {	0x74;}
}
unless(defined(&GPIO_EVNTCNT4_COMP)) {
    sub GPIO_EVNTCNT4_COMP () {	0x76;}
}
unless(defined(&GPIO_FLTR5_AMNT)) {
    sub GPIO_FLTR5_AMNT () {	0x78;}
}
unless(defined(&GPIO_FLTR5_CNT)) {
    sub GPIO_FLTR5_CNT () {	0x7a;}
}
unless(defined(&GPIO_EVNTCNT5)) {
    sub GPIO_EVNTCNT5 () {	0x7c;}
}
unless(defined(&GPIO_EVNTCNT5_COMP)) {
    sub GPIO_EVNTCNT5_COMP () {	0x7e;}
}
unless(defined(&GPIOH_OUT_VAL)) {
    sub GPIOH_OUT_VAL () {	0x80;}
}
unless(defined(&GPIOH_OUT_EN)) {
    sub GPIOH_OUT_EN () {	0x84;}
}
unless(defined(&GPIOH_OUT_OD_EN)) {
    sub GPIOH_OUT_OD_EN () {	0x88;}
}
unless(defined(&GPIOH_OUT_INVRT_EN)) {
    sub GPIOH_OUT_INVRT_EN () {	0x8c;}
}
unless(defined(&GPIOH_OUT_AUX1_SEL)) {
    sub GPIOH_OUT_AUX1_SEL () {	0x90;}
}
unless(defined(&GPIOH_OUT_AUX2_SEL)) {
    sub GPIOH_OUT_AUX2_SEL () {	0x94;}
}
unless(defined(&GPIOH_PU_EN)) {
    sub GPIOH_PU_EN () {	0x98;}
}
unless(defined(&GPIOH_PD_EN)) {
    sub GPIOH_PD_EN () {	0x9c;}
}
unless(defined(&GPIOH_IN_EN)) {
    sub GPIOH_IN_EN () {	0xa0;}
}
unless(defined(&GPIOH_IN_INV_EN)) {
    sub GPIOH_IN_INV_EN () {	0xa4;}
}
unless(defined(&GPIOH_IN_FLTR_EN)) {
    sub GPIOH_IN_FLTR_EN () {	0xa8;}
}
unless(defined(&GPIOH_IN_EVNTCNT_EN)) {
    sub GPIOH_IN_EVNTCNT_EN () {	0xac;}
}
unless(defined(&GPIOH_READ_BACK)) {
    sub GPIOH_READ_BACK () {	0xb0;}
}
unless(defined(&GPIOH_IN_AUX1_SEL)) {
    sub GPIOH_IN_AUX1_SEL () {	0xb4;}
}
unless(defined(&GPIOH_EVNT_EN)) {
    sub GPIOH_EVNT_EN () {	0xb8;}
}
unless(defined(&GPIOH_LOCK_EN)) {
    sub GPIOH_LOCK_EN () {	0xbc;}
}
unless(defined(&GPIOH_POSEDGE_EN)) {
    sub GPIOH_POSEDGE_EN () {	0xc0;}
}
unless(defined(&GPIOH_NEGEDGE_EN)) {
    sub GPIOH_NEGEDGE_EN () {	0xc4;}
}
unless(defined(&GPIOH_POSEDGE_STS)) {
    sub GPIOH_POSEDGE_STS () {	0xc8;}
}
unless(defined(&GPIOH_NEGEDGE_STS)) {
    sub GPIOH_NEGEDGE_STS () {	0xcc;}
}
unless(defined(&GPIO_FLTR6_AMNT)) {
    sub GPIO_FLTR6_AMNT () {	0xd0;}
}
unless(defined(&GPIO_FLTR6_CNT)) {
    sub GPIO_FLTR6_CNT () {	0xd2;}
}
unless(defined(&GPIO_EVNTCNT6)) {
    sub GPIO_EVNTCNT6 () {	0xd4;}
}
unless(defined(&GPIO_EVNTCNT6_COMP)) {
    sub GPIO_EVNTCNT6_COMP () {	0xd6;}
}
unless(defined(&GPIO_FLTR7_AMNT)) {
    sub GPIO_FLTR7_AMNT () {	0xd8;}
}
unless(defined(&GPIO_FLTR7_CNT)) {
    sub GPIO_FLTR7_CNT () {	0xda;}
}
unless(defined(&GPIO_EVNTCNT7)) {
    sub GPIO_EVNTCNT7 () {	0xdc;}
}
unless(defined(&GPIO_EVNTCNT7_COMP)) {
    sub GPIO_EVNTCNT7_COMP () {	0xde;}
}
unless(defined(&GPIO_MAP_X)) {
    sub GPIO_MAP_X () {	0xe0;}
}
unless(defined(&GPIO_MAP_Y)) {
    sub GPIO_MAP_Y () {	0xe4;}
}
unless(defined(&GPIO_MAP_Z)) {
    sub GPIO_MAP_Z () {	0xe8;}
}
unless(defined(&GPIO_MAP_W)) {
    sub GPIO_MAP_W () {	0xec;}
}
unless(defined(&GPIO_FE0_SEL)) {
    sub GPIO_FE0_SEL () {	0xf0;}
}
unless(defined(&GPIO_FE1_SEL)) {
    sub GPIO_FE1_SEL () {	0xf1;}
}
unless(defined(&GPIO_FE2_SEL)) {
    sub GPIO_FE2_SEL () {	0xf2;}
}
unless(defined(&GPIO_FE3_SEL)) {
    sub GPIO_FE3_SEL () {	0xf3;}
}
unless(defined(&GPIO_FE4_SEL)) {
    sub GPIO_FE4_SEL () {	0xf4;}
}
unless(defined(&GPIO_FE5_SEL)) {
    sub GPIO_FE5_SEL () {	0xf5;}
}
unless(defined(&GPIO_FE6_SEL)) {
    sub GPIO_FE6_SEL () {	0xf6;}
}
unless(defined(&GPIO_FE7_SEL)) {
    sub GPIO_FE7_SEL () {	0xf7;}
}
unless(defined(&GPIOL_EVNTCNT_DEC)) {
    sub GPIOL_EVNTCNT_DEC () {	0xf8;}
}
unless(defined(&GPIOH_EVNTCNT_DEC)) {
    sub GPIOH_EVNTCNT_DEC () {	0xfc;}
}
unless(defined(&GPIO_ATOMIC_VALUE)) {
    sub GPIO_ATOMIC_VALUE {
	my($pin,$feature) = @_;
	eval q((($feature) ? ((0<< (16+ ($pin))) | (1<< ($pin))) : ((1<< (16+ ($pin))) | (0<< ($pin)))));
    }
}
1;
